www.kersemi.com 1 irfr110, irfu110, sihfr110, sihfu110 vishay siliconix features ? dynamic dv/dt rating ? repetitive avalanche rated ? surface mount (irfr110/sihfr110) ? straight lead (irfu110/sihfu110) ? available in tape and reel ? fast switching ? ease of paralleling ? lead (pb)-free available description third generation power mosfet s from vishay provide the designer with the best combi nation of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the dpak is designed for su rface mounting using vapor phase, infrared, or wave soldering techniques. the straight lead version (irfu/sihfu series) is for through-hole mounting applications. power dissipation levels up to 1.5 w are possible in typical surcace mount applications. note a. see device orientation. product summary v ds (v) 100 r ds(on) ( )v gs = 10 v 0.54 q g (max.) (nc) 8.3 q gs (nc) 2.3 q gd (nc) 3.8 configuration single n - c hannel m os fet g d s dpak (to-252) ipak (to-251) a v aila b le rohs* compliant ordering information package dpak (to-252) dpak (to-252) d pak (to-252) dpak (to-252) ipak (to-251) lead (pb)-free irfr110pbf IRFR110TRlpbf a IRFR110TRpbf a IRFR110TRrpbf a irfu110pbf sihfr110-e3 sihfr110tl-e3 a sihfr110t-e3 a sihfr110tr-e3 a sihfu110-e3 snpb irfr110 IRFR110TRl a IRFR110TR a - irfu110 sihfr110 sihfr110tl a sihfr110t a -sihfu110 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 100 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 4.3 a t c = 100 c 2.7 pulsed drain current a i dm 17 linear derating factor 0.20 w/c linear derating factor (pcb mount) e 0.020 single pulse avalanche energy b e as 100 mj repetitive avalanche current a i ar 4.3 a repetitive avalanche energy a e ar 2.5 mj maximum power dissipation t c = 25 c p d 25 w maximum power dissipation (pcb mount) e t a = 25 c 2.5 peak diode recovery dv/dt c dv/dt 5.5 v/ns
www.kersemi.com 2 irfr110, irfu110, sihfr110, sihfu110 notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 8.1 mh, r g = 25 , i as = 4.3 a (see fig. 12). c. i sd 5.6 a, di/dt 75 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. e. when mounted on 1? square pcb (fr-4 or g-10 material). note a. when mounted on 1? square pcb (fr-4 or g-10 material). operating junction and st orage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) for 10 s 260 d thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja - 110 c/w maximum junction-to-ambient (pcb mount) a r thja -50 maximum junction-to-case (drain) r thjc -5.0 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 100 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.13 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 100 v, v gs = 0 v - - 25 a v ds = 80 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 2.6 a b - - 0.54 forward transconductance g fs v ds = 50 v, i d = 2.6 a 1.6 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 180 - pf output capacitance c oss -80- reverse transfer capacitance c rss -15- total gate charge q g v gs = 10 v i d = 5.6 a, v ds = 80 v, see fig. 6 and 13 b -- 8.3 nc gate-source charge q gs -- 2.3 gate-drain charge q gd -- 3.8 turn-on delay time t d(on) v dd = 50 v, i d = 5.6 a, r g = 24 , r d = 8.4 , see fig. 10 b -6.9- ns rise time t r -16- turn-off delay time t d(off) -15- fall time t f -9.4- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- d s g
www.kersemi.com 3 irfr110, irfu110, sihfr110, sihfu110 notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 25 c fig. 2 -typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --4.3 a pulsed diode forward current a i sm --17 body diode voltage v sd t j = 25 c, i s = 4.3 a, v gs = 0 v b --2.5v body diode reverse recovery time t rr t j = 25 c, i f = 5.6 a, di/dt = 100 a/s b - 100 200 ns body diode reverse recovery charge q rr - 0.44 0.88 c forward turn-on time t on intrinsic turn-on time is negligib le (turn-on is dominated by l s and l d ) specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit s d g
www.kersemi.com 4 irfr110, irfu110, sihfr110, sihfu110 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
www.kersemi.com 5 irfr110, irfu110, sihfr110, sihfu110 fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circui t fig. 12b - unclamped inductive waveforms p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t. l v ds + - v dd a 10 v v ary t p to o b tain re qu ired i as i as v ds v dd v ds t p
www.kersemi.com 6 irfr110, irfu110, sihfr110, sihfu110 fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
www.kersemi.com 7 irfr110, irfu110, sihfr110, sihfu110 fig. 14 -for n-channel p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs = 10 v* v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor current d = p. w . period + - + + + - - - * v gs = 5 v for logic level devices and 3 v drive devices peak diode recovery dv/dt test circuit r g v dd ? dv/dt controlled by r g ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t. circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer
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